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1 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o february 2004 2004 integrated device technology, inc. dsc-6547/2 c IDT74SSTU32864D commercial temperature range 1:1 and 1:2 registered buffer with 1.8v sstl i/o description: the sstu32864d is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7v to 1.9v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8v cmos drivers that have been optimized to drive the ddr2 dimm load. the sstu32864d operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high and clk going low. the c0 input controls the pinout configuration of the 1:2 pinout from the a configuration (when low) to b configuration (when high). the c1 input controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when high). this device supports low-power standby operation. when the reset input ( reset ) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs are forced low. the lvcmos reset and cx inputs must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 dimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the sstu32864d must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. the device monitors both d cs and csr inputs and will gate the outputs from changing states when both d cs and csr inputs are high. if either d cs or csr input is low, the device will function normally. the reset input has priority over the d cs control and will force the inputs low. if the d cs control functionality is not desired, then the csr input can be hard- wired to ground, in which case the set-up time requirement for d cs would be the same as for the other d data inputs. applications: ? along with the cspu877/a, zero delay pll clock buffer, provides complete solution for ddr2 dimms features: ? 1.8v operation ? sstl_18 style clock and data inputs ? differential clk input ? control inputs compatible with lvcmos levels ? flow-through architecture for optimum pcb design ? latch-up performance exceeds 100ma ? esd >2000v per mil-std-883, method 3015; >200v using machine model (c = 200pf, r = 0) ? improved setup and hold timing ? available in 96-pin lfbga package the idt logo is a registered trademark of integrated device technology, inc.
2 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o functional block diagram (1:2) o 1 qx a qx b r 1d c1 reset clk clk v ref dx dcke dodt dcs to 10 other channels csr r 1d c1 r 1d c1 r 1d c1 qcs a qcs b qodt a qodt b qcke a qcke b
3 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o pin configuration (type a) 96-pin lfbga 1:2 register (type a, frontside) top view pin configuration (type b) 96-pin lfbga 1:2 register (type b, backside) top view 6 5 4 3 2 1 ab c de f g hj k lmnprt q2b q3b q5b q6b q8b q9b z oh qcsb qcsa qodtb qckeb q13b q14b v dd v ref d2 d3 d5 d6 clk reset d8 d9 d10 d11 q2a q3a q5a q6a q8a q9a z ol qodta qckea q13a q14a nc clk c0 c1 v dd v ref dcke nc nc nc nc nc nc nc nc nc nc nc nc dodt gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd dcs csr q10b q11b q10a q11a q12b q12a nc d12 d14 d13 6 5 2 1 ab c def g h j k lmnprt q13b q10b q9b q8b qcsb qcsa q6b q5b z oh z ol qodtb qckeb q4b q3b q2b q1b d13 d12 d9 d8 d6 d5 clk reset d4 d3 d2 d1 q13a q10a q9a q8a q6a q5a qodta qckea q4a q3a q2a q1a nc clk c0 c1 dcke nc nc nc nc nc nc nc nc nc nc nc dodt nc 4 3 v dd v ref v dd v ref gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd dcs csr q12b q12a nc d10
4 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o functional block diagram (1:1) o 1 qx r 1d c1 reset clk1 clk1 v ref dx dcke dodt dcs to 21 other channels csr qotd r 1d c1 qcs r 1d c1 qcke r 1d c1
5 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o pin configuration abcdefghjklmnprt 6 5 4 3 2 1 96-pin lfbga 1:1 register top view 96 ball lfbga package attributes 6 5 2 1 ab c def g hj k lmnprt q15 q16 q17 q18 z ol nc qcs nc q19 q20 q21 q22 d2 d3 d5 d6 clk reset d8 d9 d10 d11 q2 q3 q5 q6 z oh qodt qcke q8 q9 q10 q11 nc dcs clk c0 c1 dcke nc dodt nc d15 d16 d17 d18 d19 d20 d21 d22 4 3 v dd v ref v dd v ref gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd gnd gnd v dd v dd csr q23 q24 q25 q12 q13 q14 d23 d24 d25 nc d12 d13 d14 *rows 3 and 4 are reserved for v dd and gnd.
6 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o function table (each flip-flop) (1) inputs qx q cs x qodtx, qckex reset d cs csr clk clk dx, dodt, dcke outputs output outputs hll llll hll hhlh h l l l or h l or h x q 0 (2) q 0 (2) q 0 (2) hlh llll hlh hhlh h l h l or h l or h x q 0 (2) q 0 (2) q 0 (2) hh l llhl hh l hhhh h h l l or h l or h x q 0 (2) q 0 (2) q 0 (2) hhh lq 0 (2) hl hhh hq 0 (2) hh h h h l or h l or h x q 0 (2) q 0 (2) q 0 (2) l x or floating x or floating x or floating x or floating x or floating l l l notes: 1. h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2. output level before the indicated steady-state conditions were established. mode select c 0 c 1 device mode 0 0 1:1 25-bit to 25-bit 0 1 1:2 14-bit to 28-bit, front (type a) 1 0 reserved 1 1 1:2 14-bit to 28-bit, back (type b)
7 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o terminal functions (all pins) terminal electrical name characteristics description gnd ground input ground v dd 1.8v nominal power supply voltage v ref 0.9v nominal input reference voltage z oh (1) input reserved for future use z ol (1) input reserved for future use clk differential input positive master clock input clk differential input negative master clock input c x lvcmos input configuration control inputs reset lvcmos input asynchronous reset input. resets registers and disables v ref data and clock differential-input receivers. csr , d cs sstl_18 input chip select inputs. disables outputs dx switching when both inputs are high. dx sstl_18 input data input. clocked in on the crossing of the rising edge of clk and the falling edge of clk . dodt sstl_18 input the outputs of this register bit will not be suspended by the d cs and csr controls dcke sstl_18 input the outputs of this register bit will not be suspended by the d cs and csr controls q x 1.8v cmos data outputs that are suspended by the d cs and csr controls q cs x 1.8v cmos data output that will not be suspended by the d cs and csr controls qodtx 1.8v cmos data output that will not be suspended by the d cs and csr controls qckex 1.8v cmos data output that will not be suspended by the d cs and csr controls absolute maximum ratings (1) symbol description max. unit v dd supply voltage range ?0.5 to 2.5 v v i (2,3) input voltage range ?0.5 to 2.5 v v o (2,3) output voltage range ?0.5 to v dd +0.5 v i ik input clamp current v i < 0 50 ma v i > v dd i ok output clamp current v o < 0 50 ma v o > v dd i o continuous output current, 50 ma v o = 0 to v dd v dd continuous current through each 100 ma v dd or gnd t stg storage temperature range ?65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. 3. this value is limited to 2.5v maximum. note: 1. the signals will be left unconnected.
8 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o operating characteristics, t a = 25oc (1,2) symbol parameter min. typ. max. unit v dd supply voltage 1.7 ? 1.9 v v ref reference voltage 0.49 * v dd 0.5 * v dd 0.51 * v dd v v tt termination voltage v ref ? 40mv v ref v ref + 40mv v v i input voltage 0 ? v dd v v ih ac high-level input voltage data inputs v ref + 250mv ? ? v v il ac low-level input voltage data inputs ? ? v ref ? 250mv v v ih dc high-level input voltage data inputs v ref + 125mv ? ? v v il dc low-level input voltage data inputs ? ? v ref ? 125mv v v ih high-level input voltage reset , cx 0.65 * v dd ??v v il low-level input voltage reset , cx ? ? 0.35 * v dd v v icr common mode input voltage clk, clk 0.675 ? 1.125 v v id differential input voltage clk, clk 600 ? ? mv i oh high-level output current ? ? tbd ma i ol low-level output current ? ? tbd t a operating free-air temperature 0 ? 70 c notes: 1. the reset and cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. the differential inputs must not be floating unless reset is low. symbol parameter test conditions min. typ. max. unit v oh v dd = 1.7v to 1.9v, i oh = ? tbd ma tbd ? ? v v ol v dd = 1.7v to 1.9v, i ol = tbd ma ? ? tbd v i i all inputs v i = v dd or gnd ? ? 5 a i dd static standby i o = 0, v dd = 1.9v, reset = gnd ? ? 100 a static operating i o = 0, v dd = 1.9v, reset = v dd , v i = v ih (ac) or v il (ac) ? ? tbd ma i ddd dynamic operating i o = 0, v dd = 1.8v, reset = v dd , v i = v ih (ac) or v il (ac) ,??? a/clock (clock only) clk and clk switching 50% duty cycle. mhz i o = 0, v dd = 1.8v, reset = v dd , 1:1 mode ? ? ? dynamic operating v i = v ih (ac) or v il (ac) , clk and clk switching at a/clock (per each data input) 50% duty cycle. one data input switching at 1:2 mode ? ? ? mhz/data half clock frequency, 50% duty cycle. input data inputs v i = v ref 250mv 2.5 ? 3.5 c i clk and clk v icr = 0.9v, v id = 600mv 2 ? 3 pf reset v i = v dd or gnd ? ? ? dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v dd = 1.8v 0.1v
9 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o timing requirements over recommended operating free-air temperature range v dd = 1.8v 0.1v symbol parameter min. max. unit f clock clock frequency ? 270 mhz tw pulse duration, clk, clk high or low 1 ? ns t act (1,2) differential inputs active time ? tbd ns t inact (1,3) differential inputs inactive time ? tbd ns d cs before clk , clk , csr high 0.7 ? t su setup time d cs before clk , clk , csr low 0.5 ? ns dodt, csr , data, and dcke before clk , clk 0.5 ? t h hold time data, d cs , csr , dcke, and dodt after clk , clk 0.5 ? ns notes: 1. this parameter is not production tested. 2. data and v ref inputs must be low a minimum time of t act max, after reset is taken high. 3. data, v ref , and clock inputs must be held at valid levels (not floating) a minimum time of t inact max, after reset is taken low. switching characteristics over recommended free-air operating range (unless otherwise noted) (1) v dd = 1.8v 0.1v symbol parameter min max. unit f max 270 ? m h z t pdm (2) clk and clk to q 1.41 (3) 2.15 (3) ns t pdmss (2,4) clk and clk to q (simultaneous switching) ? 2.35 (3) ns t rphl reset to q ? 3 ns dv/dt_r output slew rate from 20% to 80% 1 4 v/ns dv/dt_f output slew rate from 20% to 80% 1 4 v/ns dv/dt_ ? (5) output slew rate from 20% to 80% ? 1 v/ns notes: 1. see test circuits and waveforms. 2. includes 350ps of test load transmission line delay. 3. for reference only. final values to be determined. 4. this parameter is not production tested. 5. difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate).
10 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o c l = 30 pf (1) r l = 1k ? dut out r l = 100 ? clk inputs t l = 50 ? t l = 350ps, 50 ? test point v dd 0v v dd /2 lvcmos reset input i dd v dd /2 t inact t act 10% 90% (2) clk v icr v id t plh t phl output v oh v ol v icr v tt v tt v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output v icr v id v icr input t w v ref v ih v il v ref input v icr v id t su t h clk clk v dd r l = 1k ? test point test point clk clk clk test circuits and waveforms (v dd = 1.8v 0.1v) voltage waveforms - pulse duration notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0ma 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v dd /2 6. v ih = v ref + 250mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600mv. 9. t plh and t phl are the same as t pdm . load circuit voltage waveforms - setup and hold times voltage waveforms - propagation delay times voltage waveforms - propagation delay times voltage and current waveforms inputs active and inactive times
11 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o c l = 10 pf (1) (1) r l = 50 ? dut out test point v dd v oh 80% 20% v ol output dv_f dt_f c l = 10 pf r l = 50 ? dut out test point v ol 20% 80% v oh output dv_r dt_r test circuits and waveforms (v dd = 1.8v 0.1v) notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). load circuit: high-to-low slew-rate adjustment voltage waveforms: high-to-low slew-rate adjustment load circuit: low-to-high slew-rate adjustment voltage waveforms: low-to-high slew-rate adjustment
12 commercial temperature range IDT74SSTU32864D 1:1 and 1:2 registered buffer with 1.8v sstl i/o ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx xxx xx package device type temp. range bf bfg low profile, fine pitch, ball grid array very fine pitch ball grid array, green 74 1:1 and 1:2 registered buffer with 1.8v sstl i/o 0c to +70c sstu 864d 32 xx family extra wide

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